-
7) and UCIe (emerging Chiplets standard). The Senior Principal Analog Design Engineer will take a Technical Leadership role on the PMA design team as part of a SERDES Product Team. Requirements
-
methodologies and develop new ones that leverage Cadence technology and services. Take part in technical campaigns to enable our customers to adopt existing and new technologies and solutions. Requirements
-
cooperatively in a team environment BEng, MEng or PhD Cadence tool experience and design experience at >10Gbps and in <40nm technologies Lab test experience as part of silicon evaluation is advantageous Interest
Enter an email to receive alerts for PhD-carbon dioxide removal positions in germany